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HY57V643220C
4 Banks x 512K x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V643220C is organized as 4banks of 524,288x32. HY57V643220C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.)
FEATURES
* * * JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 Internal four banks operation * * * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst * - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks Burst Read Single Write operation
* *
ORDERING INFORMATION
Part No.
HY57V643220C(L)T-47 HY57V643220C(L)T-5 HY57V643220C(L)T-55 HY57V643220C(L)T-6 HY57V643220C(L)T-7 HY57V643220C(L)T-8 HY57V643220C(L)T-P HY57V643220C(L)T-S
Clock Frequency
212MHz 200MHz 183MHz 166MHz 143MHz 125MHz 100MHz 100MHz
Power
Organization
Interface
Package
Normal/ Low Power
4Banks x 512Kbits x32
LVTTL
400mil 86pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.8/Aug. 02 1
HY57V643220C
PIN CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM 0 /W E /C A S /R A S /C S NC BA0 BA1 A 1 0 /A P A0 A1 A2 DQM 2 VDD NC DQ 16 VSSQ DQ 17 DQ 18 VDDQ DQ 19 DQ 20 VSSQ DQ 21 DQ 22 VDDQ DQ 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ 15 VSSQ DQ 14 DQ 13 VDDQ DQ 12 DQ 11 VSSQ DQ 10 DQ9 VDDQ DQ8 NC VSS DQM 1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM 3 VSS NC DQ 31 VDDQ DQ 30 DQ 29 VSSQ DQ 28 DQ 27 VDDQ DQ 26 DQ 25 VSSQ DQ 24 VSS
8 6 p in T S O P II 4 0 0 m il x 8 7 5 m il 0 .5 m m p in p itc h
PIN DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A10 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE DQM0~3 DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ NC
Rev. 0.8/Aug. 02
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HY57V643220C
FUNCTIONAL BLOCK DIAGRAM 512Kbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic & Timer Refresh Counter
CLK
Row Active
512Kx32 Bank 3 Row Pre Decoder 512Kx32 Bank 2 X decoder 512Kx32 Bank 1 X decoder 512Kx32 Bank 0 X decoder DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate
CKE CS State Machine RAS CAS WE DQM0 DQM1 DQM2 DQM3
X decoder
Memory Cell Array
Column Active
Column Pre Decoder Y decoder
DQ30 DQ31
Bank Select
Column Add Counter
A0 A1 Address buffers A10 BA0 BA1
Address Register Burst Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.8/Aug. 02
3
HY57V643220C
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 . 10 Rating C C V V mA W C Sec Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70C)
Parameter Power Supply Voltage Input high voltage Input low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 VSSQ - 0.3 Typ. 3.3 3.0 0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1,2 1,3 1,4
Note : 1.All voltages are referenced to VSS = 0V 2.VDD/VDDQ(min) is 3.15V for HY57V643220C(L)T-47/5/55/6 3.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration with no input clamp diodes 4.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration with no input clamp diodes
AC OPERATING CONDITION (TA=0 to 70C, 3.0V VDD 3.6V, VSS=0V - Note1)
Parameter AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 30 Unit V V ns V pF 2 Note
Note : 1.3.15V VDD 3.6V is applied for HY57V643220C(L)T-47/5/55/6 2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit
Rev. 0.8/Aug. 02
4
HY57V643220C
CAPACITANCE (TA=25xC, f=1MHz, VDD=3.3V)
Parameter Input capacitance CLK A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 Data input / output capacitance DQ0 ~ DQ31 Pin Symbol CI1 CI2 CI/O Min 2.5 2.5 4 Max 3.5 3.8 6.5 Unit pF pF pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500
RT=50
Output 30pF
Output
Z0 = 50
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage ILI ILO VOH VOL Symbol Min. -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -2mA IOL = +2mA
Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.8/Aug. 02
5
HY57V643220C
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Speed Parameter Symbol Test Condition -47 Burst Length=1, One bank active tRAS tRAS(min), tRP tRP(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = -5 -55 -6 -7 -8 -P -S Unit Note
Operating Current
IDD1
220
200
190
180
170
150
150
150
mA
1
Precharge Standby Current in power down mode
IDD2P IDD2PS
2 mA 2
Precharge Standby Current in non power down mode
IDD2N
CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK =
15 mA 10 3 mA 3
IDD2NS IDD3P IDD3PS
Active Standby Current in power down mode
IDD3N Active Standby Current in non power down mode IDD3NS
CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = stable
40 mA 25 290 160 260 280 160 250 260 160 235 240 160 220 2 mA 1 4 210 160 210 180 160 190 180 160 210 190 mA 2 3 180 mA 1
Input signals are
CL=3 CL=2
Burst Mode Operating Current Auto Refresh Current
IDD4
tCK tCK(min), tRAS tRAS(min), IOL=0mA All banks active tRRC tRRC(min), 2 banks active CKE 0.2V
IDD5
Self Refresh Current
IDD6
Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V643220CT-47/5/55/6/7/8/P/S 4.HY57V643220CLT-47/5/55/6/7/8/P/S
Rev. 0.8/Aug. 02
6
HY57V643220C
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-47 Parameter Symbol Min System clock cycle time CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 4.7 1000 10 1.65 1.65 1.5 1.3 0.8 1.3 0.8 1.3 0.8 1.3 0.8 1 4.5 6 4 6 10 2 2 1.5 1.5 1 1.5 1 1.5 1 1.5 1 1 4.5 6 4.5 6 Max Min 5 1000 10 2.25 2.25 2 1.5 1 1.5 1 1.5 1 1.5 1 1 5 6 5 6 Max Min 5.5 1000 10 2.5 2.5 2 1.5 1 1.5 1 1.5 1 1.5 1 1 5.5 6 5.5 6 Max Min 6 1000 10 3 3 2 1.75 1 1.75 1 1.75 1 1.75 1 1 5.5 6 5.5 6 Max Min 7 1000 -10 3 3 2 2 1 2 1 2 1 2 1 1 6 6 6 6 Max Min 8 1000 10 3 3 2 2 1 2 1 2 1 2 1 1 6 6 6 6 Max Min 10 1000 12 3 3 2 2 1 2 1 2 1 2 1 1 6 6 6 6 Max Min 10 1000 ns ns ns ns 2 CAS Latency = 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 3 1 1 1 1 1 1 1 1 1 1 Max ns -5 -55 -6 -7 -8 -P -S Unit Note
Clock high pulse width Clock low pulse width Access time from clock Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time CLK to data output in high Z-time CAS Latency = 3 CAS Latency = 2 CAS Latency = 3
Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.8/Aug. 02
7
HY57V643220C
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
-47 Parameter Symbol Min Operation RAS cycle time Auto Refresh RAS to CAS delay RAS active time RAS precharge time RAS to RAS bank active delay CAS to CAS delay Write command to data-in delay Data-in to precharge command Data-in to active command DQM to data-out Hi-Z DQM to data-in mask MRS to new command Precharge to data output Hi-Z tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD 51.7 14.1 37.6 14.1 2 1 0 1 4 2 0 2 3 1 1 100K 64 55 15 38.7 15 2 1 0 1 4 2 0 2 3 2 1 1 100 K 64 55 16.5 38.7 16.5 2 1 0 1 4 2 0 2 3 2 1 1 100 K 64 60 18 42 18 2 1 0 1 4 2 0 2 3 2 1 1 100 K 64 63 20 42 20 2 1 0 1 4 2 0 2 3 2 1 1 100 K 64 64 20 48 20 2 1 0 1 4 2 0 2 3 2 1 1 100 K 64 70 20 50 20 2 1 0 1 4 2 0 2 3 2 1 1 100 K 64 70 20 50 20 2 1 0 1 4 2 0 2 3 2 1 1 100 K 64 ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 tRC 51.7 Max Min 55 Max Min 55 Max Min 60 Max Min 63 Max Min 64 Max Min 70 Max Min 70 Max ns -5 -55 -6 -7 -8 -P -S Unit Note
CAS Latency = 3 tPROZ3 CAS Latency = 2 tPROZ2 tPDE tSRE tREF
Power down exit time Self refresh exit time Refresh Time
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 0.8/Aug. 02
8
HY57V643220C
DEVICE OPERATING OPTION TABLE
HY57V643220C(L)T-47
CAS Latency 212MHz(4.7ns) 200MHz(5ns) 183MHz(5.5ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 37.6ns 38.5ns 38.5ns tRC 12CLKs 11CLKs 10CLKs tRP 3CLKs 3CLKs 3CLKs tAC 4ns 4.5ns 5ns tOH 1.5ns 1.5ns 2ns
HY57V643220C(L)T-5
CAS Latency 200MHz(5ns) 183MHz(5.5ns) 166MHz(6ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 38.5ns 38.5ns 7CLKs tRC 11CLKs 10CLKs 10CLKs tRP 3CLKs 3CLKs 3CLKs tAC 4.5ns 5ns 5.5ns tOH 1.5ns 2ns 2ns
HY57V643220C(L)T-55
CAS Latency 183MHz(5.5ns) 166MHz(6ns) 143MHz(7ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 7CLKs 6CLKs tRC 10CLKs 10CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5ns 5.5ns 5.5ns tOH 2ns 2ns 2ns
HY57V643220C(L)T-6
CAS Latency 166MHz(6ns) 143MHz(7ns) 125MHz(8ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 6CLKs 6CLKs tRC 10CLKs 9CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.5ns 5.5ns 6ns tOH 2ns 2ns 2.5ns
HY57V643220C(L)T-7
CAS Latency 143MHz(7ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.5ns 6ns 6ns tOH 2ns 2ns 2ns
HY57V64322C(L)T-8
CAS Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) 3CLKs 2CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs tRAS 6CLKs 5CLKs 4CLKs tRC 9CLKs 7CLKs 6CLKs tRP 3CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2ns 2ns 2.5ns
Rev. 0.8/Aug. 02
9
HY57V643220C
HY57V643220C(L)T- P
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2ns 2.5ns 2.5ns
HY57V643220C(L)T- S
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2ns 2.5ns 2.5ns
Rev. 0.8/Aug. 02
10
HY57V643220C
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Entry Self Refresh1 Exit H H H H H L H X L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit H L L L H V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X L L L H X L H X L L L X L L L X H L H X X H L X V X X X X X L L H L X X L X X X A9 Pin High (Other Pins OP code) V X L H L L X CA H H X X L H L H X CA H L V CKEn-1 H H H CKEn X X L X L H L H H H H X RA L V V CS L H RAS L X CAS L X WE L X X X DQM X
ADDR
A10/ AP OP code
BA
Note
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don't care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation
Rev. 0.8/Aug. 02
11
HY57V643220C
PACKAGE INFORMATION
400mil 86pin Thin Small Outline Package
Unit : mm(inch)
22.327(0.8790) 22.149(0.8720)
11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 1.194(0.0470) 0.991(0.0390)
0.50(0.0197)
0.21(0.008) 0.18(0.007)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. 0.8/Aug. 02
12

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